Photonic GPU Index

Akhetonics describes an all-optical cross-domain processor using photonic integrated circuits at mature 90 nm, 130 nm, and 250 nm nodes. The technology page states an efficiency ambition of 10× to 100× versus electronic tensor processors and does not publish a product throughput.

LRZ's 21 April 2026 report measured two generations of Q.ANT Native Processing Units. Generation 2 reached 500 million operations per second per channel, 4 billion per second across eight channels. Cards drew 25 W and 100 W.

APS Physics describes Lightelligence's Photonic Arithmetic Computing Engine as a photonic-electronic chip for Ising optimization. On the tasks shown, including a noisy image reconstruction, it solved problems 500 times faster than a modern GPU.

Lightmatter's 9 April 2025 note describes a photonic processor, tied to a Nature paper, that runs ResNet, BERT, and Atari reinforcement learning. It states 65.5 trillion ABFP16 operations per second, 78 W electrical, and 1.6 W optical.

Lumai's product page says Iris Nova runs Llama 8B and 70B and is available for datacenter evaluation. It states matrix multiplies up to 2048 by 2048 at INT4/INT8-equivalent precision, up to 100 TOPS per watt, and 1 ExaOPS inside a 10 kW budget.

Neurophos says the Tulkas T100 optical processing unit targets inference prefill and ships in 2028 on standard CMOS. Its pages disagree: one table lists 1,400 TOPS/W and 4.2 ExaOPS, another lists 235 TOPS/W. No independent measurement is cited.

Q.ANT's product page states the Native Processing Server is a 19-inch photonic co-processor in operation at LRZ and Jülich. Generation 2 is specified at 8 GOPS sustained on nonlinear functions, with a PCIe NPU card and a CPU simulation SDK.

Avicena's technology page says LightBundle uses microLED arrays and multi-core fiber for links under 1 pJ/bit beyond 10 meters. At 4 Gbps per lane and 50 µm pitch it states density above 2 Tbps/mm.

Ayar Labs describes TeraPHY as a UCIe-compliant optical I/O chiplet with 8 Tbps bidirectional bandwidth, 10 ns chiplet latency excluding fiber flight time, and BER below 1e-12. The same page also states 4 Tbps per chiplet.

Broadcom's Bailly release lists 6.4T-FR4 SCIP optical engines and the Broadcom Fiber Connector on the 51.2 Tbps co-packaged switch.

Broadcom states the Bailly co-packaged switch at 51.2 Tbps, with eight 6.4 Tbps silicon-photonics engines and 128 ports of 400G FR4 in a 4RU air-cooled system.

Broadcom's investor release describes Tomahawk 6 Davisson as a 102.4 Tbps co-packaged optics switch, with 16 optical engines of 6.4 Tbps and 200 Gbps per link. The photonic engines are described as TSMC COUPE-based.

The July 2025 Celestial AI paper describes a Photonic Fabric Appliance with up to 32 TB of shared memory and 115 Tbps of all-to-all switching. Throughput gains versus DGX-H100 are CelestiSim results, not a measured shipping cluster.

Celestial AI's Hot Interconnects 2025 slides state a Gen1 Photonic Fabric chiplet at 14.4 Tbps and a module at 7.2 Tb/s. That is a different figure from the 115 Tbps appliance in the July 2025 paper.

Ciena states the Vesta 200 6.4T CPX as a 200G-per-lane pluggable co-packaged engine aimed at 100T and 200T switch ASICs, and the first Ciena product after acquiring Nubis.

Lightmatter's Passage page specifies the L200 at 32 to 64 Tbps of aggregate co-packaged bandwidth using 112G PAM4. Sibling products on that page include the L20 at 12.8 Tbps and the M1000 EVK at 114 Tbps across 4,000 mm².

Marvell's release states a 6.4T 3D silicon-photonics engine with 32 channels of 200G electrical and optical, and 30 percent lower power per bit than its 100G devices.

NVIDIA states Quantum-X Photonics at 115 Tb/s on 144 ports of 800 Gb/s InfiniBand, with 14.4 teraflops of in-network SHARP, for early 2026.

NVIDIA's co-packaged optics post states liquid-cooled Spectrum SN6800 at 409.6 Tb/s across 512 ports of 800 Gb/s, on Spectrum-6, for the second half of 2026.

The same NVIDIA post states liquid-cooled Spectrum SN6810 at 102.4 Tb/s across 128 ports of 800 Gb/s.

Ranovus states the Odin photonic engine scales from 800 Gbps to 3.2 Tbps at 100 Gbps per wavelength, with 0.4 ns protocol-agnostic latency and reach from 10 m to 2 km.

Salience Labs specifies the OC-32M as a 32×32 non-blocking optical switch with 10 ns port-to-port latency, under 2 dB insertion loss, under 300 µs reconfiguration, and under 1 W per port. The company announced a $125 million Series B on 14 October 2026.

iPronics' 31 March 2025 release describes ONE-32 as a 32-port silicon-photonics optical circuit switch in 1U, with latency under 30 ns and reconfiguration under 300 microseconds.

AIM Photonics is a U.S. Manufacturing Innovation Institute offering silicon-photonics design enablement, multi-project wafer fabrication, and electronic-photonic test, assembly, and packaging. Its public homepage does not publish a process bandwidth.

DustPhotonics' product page, which says the company is now part of Credo, lists silicon-photonics PICs for retimed, linear-pluggable, and linear-receive transceivers. It does not publish a lane rate or energy figure.

GlobalFoundries says GF Fotonix launched in 2022 at up to 100G per wavelength using PAM4. The 26 March 2025 update says generation 2 supports 200G per wavelength and adds TSVs so an electrical die can stack on the photonic die.

OpenLight's PASIC page says a DR8 platform reaches 1.6T as eight 200G channels, and states the 3.2T PIC dissipates below 2 W at 80°C, which it calculates as 0.63 pJ/bit. Lasers are heterogeneously bonded indium phosphide.

POET's Starlight page lists packaged O-band and C-band light sources at 800G, 400G, 200G, and 100G, with 4, 8, and 16 channels and monolithically integrated mux and demux.

TSMC's HPC connectivity page says its 65 nm silicon photonics technology is in volume production and that a 3D-stacked CPO demonstrator reached 200 gigabits per second optical modulation with greater than 99 percent stacking yield on engineering samples.

Tower and OpenLight's 12 March 2025 release says a 400G-per-lane modulator on Tower's PH18DA platform reached better than 3.5 dB extinction ratio at 0.6 V peak-to-peak. The same platform already supports customers at 100G and 200G per lane.

OIF-EEI-112G-RTLR-01.0 sets a 112 Gb/s PAM4 chip-to-module link from 36 to 56 GSym/s, with channel loss up to 16 dB at Nyquist.

OIF-Co-Packaging-3.2T-Module-01.0 specifies a 3.2 Tb/s co-packaged module. Sixteen modules are the building blocks for a 51.2 Tb/s switch. Line sides include 8×400GBASE-DR4 and 8×400GBASE-FR4.

Open CPX specification 1.0 defines co-packaged and near-package sockets at 6.4 Tbps (32 lanes of 212.5 Gbps) and 7.2 Tbps (36 lanes of 212.5 Gbps), for optics or copper.

The OCI MSA homepage says the group is writing an open optical interconnect for AI scale-up using NRZ modulation and wavelength division multiplexing, moving the module-centric model to a silicon-centric one. The homepage does not print a lane rate.